1. Field of the Invention
The present invention relates to a DLL circuit and a semiconductor device including the same, and more particularly relates to a DLL circuit suitable for application when a clock signal includes a jitter component, and a semiconductor device including the DLL circuit.
2. Description of Related Art
In recent years, a synchronous memory operating synchronously with a clock is widely used as a main memory of a personal computer or the like. Among synchronous memories, a DDR (Double Data Rate) synchronous memory needs to accurately synchronize input and output data with an external clock signal. Therefore, a DLL circuit for generating an internal clock synchronous with the external clock signal is essential (Japanese Patent Application Laid-open No. 2008-217947).
The external clock signal sometimes includes a jitter component. The jitter component is a fluctuation of a clock frequency, and the fluctuation has a predetermined frequency. Therefore, when the external clock signal includes a jitter component, the DLL circuit needs to cause the internal clock signal to follow the jitter of the external clock signal.
However, due to a sampling principle, an adjustment frequency of an internal clock signal, that is, a frequency exceeding a half of a sampling frequency cannot be regenerated. This means that when a jitter component included in the external clock signal exceeds one half of the sampling frequency, an internal clock signal generated by the DLL circuit cannot be caused to follow the jitter.
Further, when the jitter component exceeds one half of the sampling frequency, aliasing is generated. When the jitter component is close to an integral multiple of the sampling frequency, the DLL circuit continuously controls the internal clock signal to a wrong direction. Consequently, there was a problem that a phase of the internal clock signal is deviated greatly from a desired phase.
FIG. 6 is a waveform diagram for explaining a phenomenon that an internal clock is continuously controlled to a wrong direction.
In the example shown in FIG. 6, when a sampling frequency is fS and also when a jitter frequency is fJ, fJ>fS/2 is obtained. Further, the sampling frequency fS and the jitter frequency fJ are close to each other. In this case, a “phase delay” is determined continuously from sampling points S1 to S12, and a “phase advance” is determined continuously from a sampling point S13 until a sampling point (not shown). However, as shown in FIG. 6, a jitter component of about 11 cycles appears during an actual sampling period from the sampling points S1 to S12, and the determination of the “phase delay” for 12 consecutive times is wrong. This similarly applies to determination for the sampling point S13 and after, and the determination of the “phase advance” for a plurality of consecutive times is wrong. When the malfunction occurs, the DLL circuit continuously controls a control direction of the internal clock signal to a wrong direction. As a result, the phase is deviated greatly from a desired phase.
To solve the above problem, it is effective to take a high sampling frequency. However, adjustment of the internal clock signal requires a certain level of time, and therefore there is a limit to the sampling frequency. There is also a problem that, when the sampling frequency is set high, power consumption increases.